Electronic components such as semiconductor elements are mounted on a wiring substrate. A buildup wiring substrate is used to increase the density of wiring patterns in such a wiring substrate. The buildup wiring substrate is obtained through a buildup process that alternately stacks wiring layers and insulation layers.
Japanese Patent No. 4993739 describes one example of a buildup wiring substrate. The wiring substrate includes a wiring formation region and a peripheral region. Wiring layers and insulation layers are alternately stacked in the wiring formation region. The peripheral region surrounds the wiring formation region and includes reinforcement patterns and reinforcement posts. The reinforcement patterns are located in different layers and continuously extend along each side of the wiring substrate. The reinforcement posts are embedded in the insulation layers between the reinforcement patterns.
FIG. 16 illustrates a wiring substrate 200 of the related art. The wiring substrate 200 includes insulation layers 201, 204, and 207, reinforcement posts 202, 205, and 208, and reinforcement patterns 203, 206, and 209. The reinforcement posts 202, 205, and 208 and the reinforcement patterns 203, 206, and 209 are located in the peripheral region of the wiring substrate 200. The reinforcement posts 202, 205, and 208 are formed in the insulation layers 201, 204, and 207, respectively. The reinforcement patterns 203, 206, and 209 are arranged on the lower surfaces of the insulation layers 201, 204, and 207, respectively. The reinforcement pattern 203 continuously extends along a plane parallel to the lower surface of the insulation layer 201 to connect the reinforcement posts 202 to one another. The insulation layer 204 is stacked on the lower surface of the insulation layer 201, and the reinforcement pattern 206 continuously extends along a plane parallel to the lower surface of the insulation layer 204 to connect the reinforcement posts 205 to one another. In the same manner, the insulation layer 207 is stacked on the lower surface of the insulation layer 204, and the reinforcement pattern 209 continuously extends along a plane parallel to the lower surface of the insulation layer 207 to connect the reinforcement posts 208 to one another. In this configuration, the reinforcement patterns 203, 206, and 209 and the reinforcement posts 202, 205, and 208 increase the rigidity of the wiring substrate 200 and reduce warping of the wiring substrate 200.
In the wiring substrate 200, the reinforcement patterns 203, 206, and 209 (e.g., copper) have a coefficient of thermal expansion that differs from that of the insulation layers 201, 204, and 207 (resin). Stress resulting from the difference in the coefficient of thermal expansion (thermal stress) or an impact applied from the outside may inflict damage, such as cracking, to the insulation layers 201, 204, and 207 that have a low strength. Such damage is apt to advance at the interfaces of the reinforcement patterns 203, 206, and 209 and the insulation layers 201, 204, and 207. As a result, damage such as cracking occurs continuously along each side of the wiring substrate 200, and the insulation layers 201, 204, and 207 have a tendency to delaminate more easily from the reinforcement patterns 203, 206, and 209.